WHEN AMD attends an event to show off its new gear, you won’t come away disappointed. At this year’s Computex trade show in Taiwan, AMD’s CEO, Lisa Su, showed us what she called “the next big step forward” in advanced chip packaging. AMD has been working with TSMC and its 3DFabric technology to combine chiplet packaging with die stacking to create a 3D chiplet architecture. The first application of this will be a 3D vertical cache, stacking memory chips directly over the processing units.
We were then treated to a glimpse of a prototype chip, a Ryzen 9 5900X with 64MB 7nm SRAM chips stacked on to each core complex, tripling the amount of L3 cache to 192MB. There is over 2TB/s of bandwidth connecting this new cache, faster than the L1 cache, although latency won’t be anywhere close. The two silicon wafers use a direct copper-to-copper bond, with no microbumps (as used in Intel’s solution). AMD has dubbed this V-Cache.